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91400 rm (im) hk no.6692-1/21 ver.1.00 d2994 preliminary overview the lc86p7148 is a cmos 8-bit single chip microcontroller with one-time prom for the lc867100 series. this microcontroller has the function and the pin description of the lc867100 series mask rom version, and 48k-byte prom. qfp package are available for shipping as well as lc867100 series. it is suitable to set up first release, prototyping, developing and testing of set. features (1) option switching by prom data the option function of the lc867100 series can be specified by the prom data. lc86p7148 can be checked the functions of the trial pieces using the mass production board. (2) internal one-time prom capacity : 49152 bytes (3) internal ram capacity : 1152 bytes used prom or ram capacity are equal rom or ram capacity of mask rom version which applies lc86p7148. mask rom version prom capacity ram capacity lc867148 49152 bytes 1152 bytes lc867140 40960 bytes 1152 bytes LC867132 32768 bytes 768 bytes lc867128 28672 bytes 768 bytes lc867124 24576 bytes 768 bytes lc867120 20480 bytes 640 bytes lc867116 16384 bytes 640 bytes lc867112 12288 bytes 512 bytes lc867108 8192 bytes 512 bytes programming service we offers various services at nominal charges. these include the rom writing, the rom reading, the package stamping and the screening. contact our representative for further information. 8-bit single chip microcontroller with one-time programmable prom lc86p7148 ordering number : enn*6692 cmos ic
lc86p7148 no.6692-2/21 (4) operating supply voltage : 4.5v to 6.0v (5) instruction cycle time : 1 s to 366 s (6) operating temperature : -30 c to +70 c (7) the pin compatible with the lc867100 series mask rom devices (8) applicable mask rom version : lc867148/lc867140/LC867132/lc867128/lc867124/lc867120 /lc867116/lc867112/lc867108 (9) factory shipment : qfp80e notice for use lc86p7148 is provided for the first release and small shipping of the lc867100 series. at using, take notice of the followings. (1) a point of difference lc86p7148 and lc867100 series item lc86p7148 lc867148/40/32/28/24/20/16/12/08 operation after reset releasing the option is specified until 3ms after going to a ?h? level to the reset terminal by degrees. the program is executed from 00h of the program counter. the program is executed from 00h of the program counter immediately after going to a ?h? level to the reset terminal. operating supply voltage range (vdd) 4.5v to 6.0v 2.5v to 6.0v total output current [ ioal(2)] [ ioal(3)] power dessipation refer to ?electrical characteristics? on the semiconductor news. lc86p7148 uses 256 bytes that is addressed on 0ff00h to ffffh in the program memory as the option configuration data area. this option configuration can execute all options which lc867100 series have. next tables show the options that correspond and not correspond to lc86p7148. a kind of the option corresponding of the lc86p7148 a kind of option pins, circuits contents of the option 1. input : no pull-up mos tr. output : n-channel open drain *1 port 0 (specified in a bit) 2. input : pull-up mos tr. output : cmos *2 input/output form of input/output ports port 1 (specified in a bit) *1 1. input : programmable pull-up mos tr. output : n-channel open drain 2. input : programmable pull-up mos tr. output : cmos pull-up mos tr. of input port port 7 (specified in a bit) *1 each of p74 and p75 has no option 1. no pull-up mos tr. 2. pull-up mos tr. *1) specified in a bit. *2) specified in nibble unit. pull-up mos tr. is not provided in n-channel open drain output port.
lc86p7148 no.6692-3/21 (2) option the option data is created by the option specified program ?su86k.exe?. the created option data is linked to the program area by linkage loader ?l86k.exe?. (3) rom space lc86p7148 and lc867100 series use 256 bytes that is addressed on 0ff00h to 0ffffh in the program memory as the option specified data area. these program memory capacity are 49152 bytes that is addressed on 0000h to 0bfffh. (4) ordering information 1. when ordering the identical mask rom and prom devices simultaneously. provide an eprom containing the target memory contents together with the separate order forms for each of the mask rom and prom versions. 2. when ordering a prom device. provide an eprom containing the target memory contents together with an order form. 0ffffh 0ff00h 0efffh 0dfffh 0cfffh 0bfffh 0afffh 9fffh 8fffh 7fffh 6fffh 5fffh 4fffh 3fffh 2fffh 1fffh 0fffh 0000h option data area 256 bytes program area 48k bytes option data area program area 40k bytes lc867148 lc867140 option data area program area 32k bytes LC867132 option data area program area 28k bytes lc867128 option data area program area 24k bytes lc867124 0ffffh 0ff00h 0efffh 0dfffh 0cfffh 0bfffh 0afffh 9fffh 8fffh 7fffh 6fffh 5fffh 4fffh 3fffh 2fffh 1fffh 0fffh 0000h option data area 256 bytes program area 20k bytes option data area program area 16k bytes lc867120 lc867116 option data area program area 12k bytes lc867112 option data area program area 8k bytes lc867108
lc86p7148 no.6692-4/21 how to use (1) specification of option the lc86p7148 must be programmed after specifying option data. the option is specified by ?su86k.exe?. the specified option file and the file created by our macro assembler ?m86k.exe? are linked by our linkage loader ?l86k.exe? which creates .hex file, then the option code is put in the option specified area (0ff00h to 0ffffh) of its .hex file. (2) how to program for the eprom the lc86p7148 can be programmed by eprom programmer with attachment ; w86ep7148q recommended eprom programmer productor eprom programmer advantest r4945, r4944, r4943 andou af-9704 aval pkw-1100, pkw-3000 minato electronics model1890a ?27512 (vpp=12.5v) intel high speed programming? mode available. the address must be set to ?0 to 0ffffh? and a jumper (dasec) must be set to ?off? at programming . (3) how to use the data security function ?data security? is the disabled function to read the data of the eprom. the following is the process in order to execute the data security. 1. set ?on? the jumper of attachment. 2. program again. then eprom programmer displays the error. the error means normally activity of the data security. it is not a trouble of the eprom programmer or the lsi. notes data security is not executed when the data of all address have ?ffh? at the sequence 2 above. the programming by a sequential operation ?blank=>program=>verify? cannot be executed data security at the sequence 2 above. set to ?off? the jumper after executing the data security. w86ep7148q data security not data security
lc86p7148 no.6692-5/21 pin assignment package dimension (unit : mm) 3174 sanyo : qip-80e notes the qfp packages should be heat-soaked for 12 hours at 125 c immediately prior to mounting (this baking is called pre-baking). after pre-baking a controlled environment must be maintained until soldering. the environment must be held at a temperature of 30 c or less and a humidity level of 70% or less. please solder within 24 hours. com1/pl1 com2/pl2 com3/pl3 vss2 vdd2 p00 p01 p02 p03 p04 p05 p06 p07 p10/so0 p11/si0/sb0 p12/sck0 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 s11/pb3 s10/pb2 s9/pb1 s8/pb0 s7/pa7 s6/pa6 s5/pa5 s4/pa4 s3/pa3 s2/pa2 s1/pa1 s0/pa0 p73/int3/t0in p72/int2/t0in p71/int1 p93/da3/an11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p13/so1 p14/si1/sb1 p15/sck1 p16/buz p17/pwm0 p70/int0 res xt1/p74 xt2/p75 vss1 cf1 cf2 vdd1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7 p90/da0/an8 p91/da1/an9 p92/da2/an10 com0/pl0 v1/pl4 v2/pl5 v3/pl6 s31/pd7 s30/pd6 s29/pd5 s28/pd4 s27/pd3 s26/pd2 s25/pd1 s24/pd0 s23/pc7 s22/pc6 s21/pc5 s20/pc4 s19/pc3 s18/pc2 s17/pc1 s16/pc0 s13/pb5 s12/pb4 vss3 vdd3
lc86p7148 no.6692-6/21 system block diagram ir clock generator alu s0 ? s7 (pa) s8 ? s13 (pb) s16 ? s23 (pc) s24 ? s31 (pd) com0 ? com3(pl) prom control a15-a0 d7-d0 ta ce oe dasec prom(48kb) pc pla acc b register c register psw rar ram stack pointer port 0 watchdog timer bus interface base timer interrupt control stand-by control cf rc x?tal port 1 port 7 port 8 port 9 adc int0 - 3 nose filter dac sio0 sio1 timer 0 timer 1 real time service ram 128 b y tes lcd controller
lc86p7148 no.6692-7/21 pin description pin name i/o function description option prom mode vss1 *1 - power pin (?) - vss2 *1 - power pin (?) - vss3 *1 - power pin (?) - vdd1 *1 - power pin (+) - vdd2 *1 - power pin (+) - vdd3 *1 - power pin (+) - port0 p00 - p07 i/o 8-bit input/output port input/output in nibble units input for port 0 interrupt input for hold release pull-up resistor : provided/not provided (specified in nibble units) output form (p00 ? p07) : cmos/n-channel open drain (specified in a bit) port1 p10 - p17 i/o 8-bit input/output port input/output can be specified in bit unit other pin functions p10 sio0 data output p11 sio0 data input/bus input/output p12 sio0 clock input/output p13 sio1 data output p14 sio1 data input/bus input/output p15 sio1 clock input/output p16 buzzer output p17 timer1 output (pwm output) output form : cmos/n-channel open drain (specified in a bit) data line d0 to d7 6-bit input port other pin functions p70 : int0 input/hold release input/ n-channel tr. output for watchdog timer p71 : int1 input/hold release input p72 : int2 input/timer 0 event input p73 : int3 input with noise filter/timer 0 event input interrupt received form, vector address pull-up resistor : provided/not provided (specified in a bit) (p70, p71, p72, p73) * p74 , p75 don?t have the pull-up resistor option. rising falling rising & falling high level low level vector int0 enable enable disable enable enable 03h int1 enable enable disable enable enable 0bh int2 enable enable enable disable disable 13h int3 enable enable enable disable disable 1bh port7 p70 p71 - p73 p74 - p75 i/o i i p74 : xt1 terminal for crystal oscillation p75 : xt2 terminal for crystal oscillation power for programming prom contro l signals dasec(*2) oe (*3) ce (*4) port8 p80 ? p87 i 8-bit input port other function ad input port (8 port pins) - port9 p90 - p93 i/o 4-bit input/output port other function da output port (4 port pins) ad input port (4 port pins) -
lc86p7148 no.6692-8/21 pin name i/o function description option prom mode port a (s0/pa0 ? s7/pa7) i/o segment output terminal for lcd display can be used as a general input/output port - address input a0 to a7 port b (s8/pb0 ? s13/pb5) i/o segment output terminal for lcd display can be used as a general input/output port - address input a8 to a13 port c (s16/pc0 ? s23/pc7) i/o segment output terminal for lcd display can be used as a general input/output port - prom control signal input ta(*5) address input a14,a15 port d (s24/pd0 ? s31/pd7) i/o segment output terminal for lcd display can be used as a general input/output port - port l (com0/pl0 ? com3/pl3) i/o common output terminal for lcd display can be used as a general input port - v1/pl4 ? v3/pl6 i bias power terminal for lcd drive can be used as a general input port - res i reset pin - xt1/ p74 i input pin for 32.768khz crystal oscillation in case of non use, connect to vdd. other function a general input port p74 - xt2/p75 o ( i ) output pin for 32.768khz crystal oscillation in case of non use, should be left unconnected other function a general input port p75 - cf1 i input pin for ceramic resonator oscillation - cf2 o output pin for ceramic resonator oscillation - * all of port options can be specified in bit unit except the pull-up resistor of port 0. [notes] the vdd1, vdd2 and vdd3 terminals must be shorted electrically each other. the vss1, vss2 and vss3 terminals must be shorted electrically each other. *1 connect like the following figure to reduce noise into a vdd terminals. *2 memory select input for data security *3 output enable input *4 chip enable input *5 ta ! prom control signal input power supply vdd1 vdd2 lsi vdd3 vss1 vss2 vss3
lc86p7148 no.6692-9/21 1. absolute maximum ratings at ta=25 c, vss=vss1=vss2=vss3=0v ratings parameter symbol pins conditions v dd[v] min. typ. max. unit supply voltage vddmax vdd1, vdd2 vdd3 vdd1=vdd2= vdd3 -0.3 +7.0 lcd display voltage vlcd v1/pl6, v2/pl5 v3/pl4 vdd1=vdd2= vdd3 -0.3 vdd input voltage vi ports 71, 72, 73 ports 74 , 75 port 8, port l res -0.3 vdd+0.3 input/output voltage vio ports 0, 1 port 9 ports a, b, c, d -0.3 vdd+0.3 v ioph(1) ports 0, 1 -4 ioph(2) ports a, b, c, d -4 peak output current ioph(3) port 9 cmos output at each pins -4 ioah(1) ports 0, 1 total all pins -30 ioah(2) ports a, b total all pins -20 ioah(3) ports c, d total all pins -20 high level output current total output current ioah(4) port 9 total all pins -20 iopl(1) ports 0, 1 at each pins 20 iopl(2) ports a, b, c, d at each pins 20 iopl(3) port 9 at each pins 20 peak output current iopl(4) port 70 at each pins 15 ioal(1) ports 0, 1 total all pins 40 ioal(2) ports a, b total all pins 24 ioal(3) ports c, d total all pins 24 ioal(4) port 9 total all pins 15 low level output current total output current ioal(5) port 70 total all pins 10 ma maximum power dissipation pdmax qfp80e ta=-30 to+70c 515 mw operating temperature range topr -30 +70 storage temperature range tstg -65 +150 c notes the qfp packages should be heat-soaked for 12 hours at 125 c immediately prior to mounting (this baking is called pre-baking). after pre-baking a controlled environment must be maintained until soldering. the environment must be held at a temperature of 30 c or less and a humidity level of 70% or less. please solder within 24 hours.
lc86p7148 no.6692-10/21 2. recommended operating range at ta=-30 c to +70 c, vss=vss1=vss2=vss3=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit vdd(1) 0.98 s tcyc 400 s 4.5 6.0 operating supply voltage range vdd(2) vdd1,vdd2,vdd3 3.9 s tcyc 400 s 2.5 6.0 hold voltage vhd vdd1,vdd2,vdd3 rams and the registers hold voltage at hold mode. 2.0 6.0 vih(1) port 0 output disable 4.5-6.0 0. 4vdd +0.9 vdd vih(2) ports 1, 9 ports a, b, c, d ports 72, 73 (schmitt) output disable 4.5-6.0 0.75vdd vdd vih(3) port 70 port input/interrupt port 71 res (schmitt) output n-channel tr. off 4.5-6.0 0.75vdd vdd vih(4) port 70 watchdog timer output n-channel tr. off 4.5-6.0 0.9vdd vdd input high voltage vih(5) port 8 ports 74 , 75 using as port 4.5-6.0 0.75vdd vdd vil(1) port 0 output disable 4.5-6.0 vss 0.2vdd vil(2) ports 1, 9 ports a, b, c, d ports 72, 73 (schmitt) output disable 4.5-6.0 vss 0.25vdd vil(3) port 70 port input/interrupt port 71 res (schmitt) output n-channel tr. off 4.5-6.0 vss 0.25vdd vil(4) port 70 watchdog timer output n-channel tr. off 4.5-6.0 vss 0. 8vdd -1.0 input low voltage vil(5) port 8 ports 74 , 75 using as port 4.5-6.0 vss 0.25vdd v operation cycle time tcyc 4.5-6.0 0.98 400 s
lc86p7148 no.6692-11/21 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit fmcf(1) cf1, cf2 6mhz (ceramic resonator oscillation) refer to figure 1 4.5-6.0 5.88 6 6.12 fmcf(2) cf1, cf2 3mhz (ceramic resonator oscillation) refer to figure 1 4.5-6.0 2.94 3 3.06 fmrc rc oscillation 4.5-6.0 0.4 0.8 3.0 mhz oscillation frequency range (note 1) fsxtal xt1, xt2 32.768khz (crystal oscillation) refer to figure 2 4.5-6.0 32.768 khz tmscf(1) cf1, cf2 6mhz (ceramic resonator oscillation) refer to figure 3 4.5-6.0 0.05 0.5 tmscf(2) cf1, cf2 3mhz (ceramic resonator oscillation) refer to figure 3 4.5-6.0 0.10 1.00 ms oscillation stabilizing time period (note 1) tssxtal xt1, xt2 32.768khz (crystal oscillation) refer to figure 3 4.5-6.0 s (note 1) the oscillation constant is shown on table 1 and table 2.
lc86p7148 no.6692-12/21 3. electrical characteristics at ta=-30 c to +70 c, vss=vss1=vss2=vss3=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iih(1) port 1 port 0 without pull-up mos tr. output disable pull-up mos tr. off. vin=vdd (including the off- leak current of the output tr.) 4.5-6.0 1 iih(2) port 7 without pull-up mos tr. port 8 vin=vdd 4.5-6.0 1 iih(3) port 9 vin=vdd 4.5-6.0 1 iih(4) ports a, b, c, d, l vin=vdd 4.5-6.0 1 iih(5) res vin=vdd 4.5-6.0 1 input high current iih(6) ports 74 ,75 using as port vin=vdd 4.5-6.0 1 iil(1) port 1 port 0 without pull-up mos tr. output disable pull-up mos tr. off. vin=vss (including the off- leak current of the output tr.) 4.5-6.0 -1 iil(2) port 7 without pull-up mos tr. port 8 vin=vss 4.5-6.0 -1 iil(3) port 9 vin=vss 4.5-6.0 -1 iil(4) ports a, b, c, d, l vin=vss 4.5-6.0 -1 iil(5) res vin=vss 4.5-6.0 -1 input low current iil(6) ports 74 ,75 using as port vin=vss 4.5-6.0 -1 a voh(1) ports 0,1 of cmos output ioh=-1.0ma 4.5-6.0 vdd-1 output high voltage voh(2) port 9 of cmos output ports a, b, c, d of cmos output ioh=-1.0ma 4.5-6.0 vdd-1 vol(1) iol=10ma 4.5-6.0 1.5 vol(2) ports 0, 1 iol=1.6ma 4.5-6.0 0.4 vol(3) port 70 iol=1ma 4.5-6.0 0.4 vol(4) iol=6ma 4.5-6.0 1.5 vol(5) port 9 iol=1.2ma 4.5-6.0 0.4 vol(6) iol=8ma 4.5-6.0 1.5 output low voltage vol(7) ports a, b, c, d of cmos output iol=1.6ma 4.5-6.0 0.4 v continue.
lc86p7148 no.6692-13/21 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit vodls s0 to s13, s16 to s31 deference voltage to ideal value vlcd, 2/3vlcd, 1/3vlcd 4.5-6.0 0 0.2 lcd output regulation vodlc com0 to com3 deference voltage to ideal value vlcd, 2/3vlcd, 1/2vlcd, 1/3vlcd 4.5-6.0 0 0.2 v rlcd(1) resistance at a ladder resistor 4.5-6.0 60 lcd ladder resistor rlcd(2) resistance at a ladder resistor 1/2r mode 4.5-6.0 30 pull-up mos tr. resistor rpu ports 0, 1 ports a, b, c, d ports 70, 71, 72, 73 voh=0.9vdd 4.5-6.0 15 40 70 k ? hysteresis voltage vhis ports 0, 1 ports 70, 71, 72, 73 res output disable 4.5-6.0 0.1vdd v pin capacitance cp all pins f=1mhz unmeasurement terminals for the input are set to vss level. ta=25c 4.5-6.0 10 pf 4. serial input/output characteristics at ta=-30 c to +70 c, vss=vss1=vss2=vss3=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit cycle tckcy(1) 4.5-6.0 2 low level pulse width tckl(1) 4.5-6.0 1 input clock high level pulse width tckh(1) sck0, sck1 refer to figure 5. 4.5-6.0 1 cycle tckcy(2) 4.5-6.0 2 low level pulse width tckl(2) 4.5-6.0 1/2 tckcy serial clock output clock high level pulse width tckh(2) sck0, sck1 use pull-up resistor (1k ? ) when open drain output. refer to figure 5. 4.5-6.0 1/2 tckcy tcyc data set up time tick 4.5-6.0 0.1 serial input data hold time tcki si0,si1 sb0,sb1 data set-up to sck0, 1 data hold from sck0, 1 refer to figure 5. 4.5-6.0 0.1 output delay time (serial clock is external clock) tcko(1) 4.5-6.0 7 /12tcyc +0.2 serial output output delay time (serial clock is internal clock) tcko(2) so0, so1 sb0, sb1 use pull-up resistor (1k ? ) when open drain output. data hold from sck0, 1 refer to figure 5. 4.5-6.0 1/3tcyc +0.2 s
lc86p7148 no.6692-14/21 5. pulse input conditions at ta=-30 c to +70 c, vss=vss1=vss2=vss3=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit tpih(1) tpil(1) int0, int1 int2/t0in interrupt acceptable timer0-countable 4.5-6.0 1 tpih(2) tpil(2) int3/t0in (the noise rejection clock is selected to 1/1.) interrupt acceptable timer0-countable 4.5-6.0 2 tpih(3) tpil(3) int3/t0in (the noise rejection clock is selected to 1/16.) interrupt acceptable timer0-countable 4.5-6.0 32 tpih(4) tpil(4) int3/t0in (the noise rejection clock is selected to 1/64.) interrupt acceptable timer0-countable 4.5-6.0 128 tcyc high/low level pulse width tpil(5) res reset acceptable 4.5-6.0 200 s 6. ad converter characteristics at ta=-30 c to +70 c, vss=vss1=vss2=vss3=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit resolution nad 4.5-6.0 8 bit absolute precision (note 2) etad 4.5-6.0 1.5 lsb ad conversion time = 16 tcyc (adcr2=0) (note 3) 15. 68 (tcyc= 0.98 s) 65.28 (tcyc= 4.08 s) conversion time tcad ad conversion time = 32 tcyc (adcr2=1) (note 3) 4.5-6.0 31.36 (tcyc= 0.98 s) 130.56 (tcyc= 4.08 s) s analog input voltage range vain 4.5-6.0 vss vdd v iainh vain=vdd 4.5-6.0 1 analog port input current iainl an0 - an11 vain=vss 4.5-6.0 -1 a (note 2) absolute precision excepts quantizing error (1/2 lsb). (note 3) the conversion time means the time from executing the ad conversion instruction to setting the complete digital conversion value to the register.
lc86p7148 no.6692-15/21 7. da converter characteristics at ta=-30 c to +70 c, vss=vss1=vss2=vss3=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit resolution nda 4.5-6.0 8 bit 8 bit mode 1.0 9 bit mode 0.8 total error 9.5 bit mode 4.5-6.0 0.7 % settling time tsad (note 4) 4.5-6.0 0.5 s 8 bit mode vss vdd 9 bit mode (1) vss 1/2vdd 9 bit mode (2) 1/2vdd vdd analog output voltage range vaout da0 to da3 9.5 bit mode 4.5-6.0 1/3vdd 2/3vdd v output resistor roda (note 5) 4.5-6.0 4 k ? (note 4) settling time means the time from executing the da conversion instruction to generating the analog voltage output corresponding to the digital data on the specific port. (note 5) da data = 80h 8. current dissipation characteristics at ta=-30 c to +70 c, vss=vss1=vss2=vss3=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iddop(1) fmcf=6mhz ceramic resonator oscillation fsxtal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 1/1 divided 4.5-6.0 15 30 iddop(2) fmcf=3mhz ceramic resonator oscillation fsxtal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 1/2 divided 4.5-6.0 6 15 iddop(3) fmcf=0hz (when oscillation stops) fsxtal=32.768khz crystal oscillation system clock : rc oscillation 1/2 divided 4.5-6.0 4 13 current dissipation during basic operation (note 6) iddop(4) vdd1= vdd2= vdd3 fmcf=0hz (when oscillation stops) fsxtal=32.768khz crystal oscillation system clock : crystal oscillation internal rc oscillation stops 1/2 divided 4.5-6.0 4 9 ma continue.
lc86p7148 no.6692-16/21 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iddhalt(1) halt mode fmcf=6mhz ceramic resonator oscillation fsxtal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 1/1 divided 4.5-6.0 6 11 iddhalt(2) halt mode fmcf=3mhz ceramic resonator oscillation fsxtal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 1/2 divided 4.5-6.0 2.2 9 ma iddhalt(3) halt mode fmcf=0hz (when oscillation stops) fsxtal=32.768khz crystal oscillation system clock : rc oscillation 1/2 divided 4.5-6.0 500 1700 iddhalt(4) current dissipation in halt mode (note 6) iddhalt(5) vdd1= vdd2= vdd3 halt mode fmcf=0hz (when oscillation stops) fsxtal=32.768khz crystal oscillation system clock : crystal oscillation internal rc oscillation stops 1/2 divided 4.5-6.0 25 100 current dissipation in hold mode (note 6) iddhold(1) vdd1= vdd2= vdd3 hold mode 4.5-6.0 0.05 30 a (note 6) the currents of the output transistors and the pull-up mos transistors are ignored.
lc86p7148 no.6692-17/21 table 1. ceramic resonator oscillation recommended constant (main clock) oscillation type maker oscillator c1 c2 csa6.00mg 33pf 33pf murata cst6.00mgw on chip kbr-6.0msa 33pf 33pf pbrc6.00a(chip type) 33pf 33pf kbr-6.0mks 6mhz ceramic resonator oscillation kyocera pbrc6.00b(chip type) on chip csa3.00mg 33pf 33pf murata cst3.00mgw on chip 3mhz ceramic resonator oscillation kyocera kbr-3.0ms 47pf 47pf * both c1 and c2 must use k rank (10%) and sl characteristics. table 2. crystal oscillation guaranteed constant (sub clock) oscillation type maker oscillator c3 c4 32.768khz crystal oscillation (notes) since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the osci llation pins as possible with the shortest possible pattern length. if you use other oscillators herein, we provide no guarantee for the characteristics. figure 1 ceramic oscillation circuit figure 2 crystal oscillation circuit cf c2 c1 cf1 cf2 xt1 xt2 c4 c3 x?tal
lc86p7148 no.6692-18/21 figure 3 oscillation stable time xt1, xt2 xt1, xt2 power supply res internal rc resonator oscillation cf1, cf2 operation mode reset time vdd vdd limit 0v unfixed instruction execution mode reset tmscf tmscf valid instruction execution mode hold hold release signal internal rc resonator oscillation cf1, cf2 operation mode tssxtal tssxtal instruction execution mode ocr6=1
lc86p7148 no.6692-19/21 figure 4 reset circuit figure 5 serial input / output test condition figure 6 pulse input timing condition (note) fix the value of cres, rres that is sure to reset until 200 s, after power supply has been over inferior limit of supply voltage. c res vdd r res res so0, so1 sb0, sb1 si0 si1 sck0 sck1 tc k o tc ki t i c k tc kh tc kl tc k c y 0.5vdd 50pf 1k ?
lc86p7148 no.6692-20/21 notice for use the construction of the one-time programmable microcomputer with a blank built-in prom makes it impossible for sanyo to completely factory-test it before shipping. to probe reliability of the programmed devices, the screening procedure shown in the following figure should always be followed. it is not possible to perform a writing test on the blank prom.. 100% yield, therefore, cannot be guaranteed. keeping the dry packing the environment must be held at a temperature of 30 c or less and a humidity level of 70% or less. after opening the packing the preparation procedures shown in the following figure should always be followed prior to mounting the packages on the substrate. note that the qfp package should be heat-soaked for 12 hours at 125 c immediately prior to mounting (this baking is called pre-baking). after pre-baking, a controlled environment must be maintained until soldering. the environment must be held at a temperature of 30 c or less and a humidity level of 70% or less. please solder within 24 hours. a. shipping with a blank prom b. shipping with a programmed prom (programming the data by yourself) (programming the data by sanyo) recommended process of screening qfp writing data for program/verifying heat-soak 1505 c, 24 hr +1 -0 reading ascertain of program vdd=50.5v mounting qfp mounting baking before mounting 125 c, 12 hours baking baking before mounting 125 c, 12 hours baking
lc86p7148 no.6692-21/21 ps

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